1. Field of the Invention
This invention relates to an arrangement for reducing the access time (increasing the hit rate) by the intermediate storage of a plurality of items of data read out from a working store, in a storage system with working stores divided into storage modules.
2. Description of the Prior Art
In view of the fact that high speed working stores are very expensive and, therefore, for reasons of economy, cannot be made to be large; whereas, however, modern data processing systems require larger and larger working stores, the concept of a store hierarchy, which has long existed in respect of the relationship of working stores to periphery stores is currently frequently being applied to the working store itself. In this case, a small, relatively inexpensive but high-speed buffer store is arranged prior to a large, inexpensive but slow main store, and the entire system is organized in such a way that it is initially attempted to fulfill all accesses to the store from the buffer store. If this is not successful, the requested word which is passed on to the processor, is input, together with the entire vicinity of this word (a block), into the buffer store, and it is anticipated that the following processor accesses will then fall either into this block or into a block which has already been input into the buffer store at an earlier point.
If a word requested by the processor is found in the buffer store, this event is referred to as a hit. The number of hits, in relation to the total number of requests made by the processor to the store, is defined as the hit rate. Assuming a sufficient block length and a sufficient capacity of the buffer store, this hit rate can be close to 100%. When main and buffer stores are suitably dimensioned, a storage system of this kind has the advantage of a low access time (buffer store) and a high capacity (main store). The disadvantage of such a storage system, on the other hand, resides in the relatively high costs of the buffer store.
In order to avoid the disadvantages of the high costs of the buffer store, it is also possible to design storage systems which operate entirely without buffer stores, but which are otherwise equipped with a same basic element as working store modules arranged in one (or more than one) storage bank, with an assigned storage bank electronic unit and a common storage bank coordinator. In this configuration, certain buffer store functions are carried out by the storage bank coordinator. In a storage system of this kind, lower costs could be expected because of the omission of the buffer store, but, on the other hand, it would be necessary to accept the disadvantage that the accesses of the processor to the store would always have to be executed as direct accesses to the working store modules, and it would not be possible to exploit the advantages of the words intermediate stored in a buffer store. Therefore, the average access time in a storage system of this type would be considerably greater.
Therefore, it has also already been proposed that in a storage system which has no buffer store, i.e. one which comprises only working store modules arranged in storage banks in each case with a common storage bank electronic unit and a storage bank coordinator, and in which the word width of the stores is greater than the word width required by the processor, the access time of the entire system be reduced, in that the data which are read out in a read-out operation are, until they are overwritten by following storage operations, held in readiness on the read-out data lines between the storage bank electronic unit and the storage bank coordinator. The items of data stored during a read-out operation in the common data input and output registers of the working store modules are not erased immediately at the end of the read-out operation, but remain in intermediate storage in this register until a following access to the working store module. Notwithstanding the advantage of the substantial improvement in the access time, this measure also has a certain disadvantage, inasmuch as the read-out data intermediately stored in the common data input and output register are overwritten by each following storage operation, whether this be a write-in operation or a read-out operation, if only one common data register is, for reasons of economy, provided for write-in and read-out, although a part of this read-out data could be used for following processor requests. Thus, this imposes a certain limitation of the reduction gained in the access time.